1. Technical Field
The present invention relates to a test apparatus, a test method, and a program therefor. More particularly, the present invention relates to a test apparatus, a test method, and a program therefor for regulating a timing of a test signal to be supplied to a device under test.
2. Related Art
Conventionally, a test apparatus has input operational clock signals into a device under test, and has operated the device under test by means of the operational clock signals. That is to say, the operational clock signals are synchronized between the test apparatus and the device under test, and thus the test apparatus can supply test signals to the device under test based on the operational clock signals and can acquire output signals from the device under test based on the operational clock signals. In addition, there are the following Patent Documents as related prior art documents.
Japanese Patent Application Publication No. 1994-188635
Japanese Patent Application Publication No. 2003-149305
However, depending on a type of the device under test, the device under test generates operational clock signals by means of an independent oscillation circuit to operate independently of the test apparatus in some cases. Since operational clock signals are not synchronized between such a device under test and the test apparatus, the test apparatus cannot supply test signals to the device under test and also cannot acquire output signals from the device under test in some cases.
Moreover, when input signals input into the device under test include noises (so-called jitters) for a time component, phases of the input signals may be deviated independently of operating clocks of the device under test. In order to test admissibility for deviance of such a phase, the test apparatus has conventionally modulated test signals and input the signals into the device under test, and has tested whether the device under test operates normally. In order to realize this test, there has been conventionally used a method for setting a modifying amount of a phase for each cycle of the test signal. However, when frequency of jitter is low, since the type of modifying amounts of phase which are set for each cycle increases and thus a requirement amount of hardware resources such as a register becomes large, it is not realistic.
As a reference technique, a technique for shaping a signal waveform by means of controlling a divider with a value stored on a memory is proposed in Japanese Patent Application Publication No. 1994-188635. According to this technique, since it is preferable that the memory stores one period of data, it is possible to reduce a capacity of the memory required for waveform shaping. However, this document only shows one method for shaping a waveform and thus does not disclose how to synchronize signals by means of applying waveform shaping.
Therefore, it is an object of some aspects of the present invention to provide a test apparatus, a test method, and a program therefor which can solve the foregoing problems. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.